1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, and more particularly, it is directed to, for example, dual damascene processing of a multilevel wiring layer having a hybrid structure.
2. Related Background Art
In the manufacture of a semiconductor device having multilevel wiring lines, a multilevel wiring layer having a so-called hybrid structure has recently been widely used which includes, in an interlayer insulating film, a stack of two kinds of films of different materials, for example, a carbon-containing silicon oxide (SiOC) film and an organic insulating film, in order to produce a good dual damascene shape.
When a dual damascene method is applied to the formation of the multilevel wiring layer of the hybrid structure, there has been a problem that the organic insulating film is also easily damaged during the removal of a resist because the composition of the organic insulating film is close to the composition of the resist used for a pattern (e.g., refer to Japanese Laid Open (Kokai) 2004-319616, paragraph number (0004)). In order to avoid such a problem, a method has heretofore been used which forms a via pattern after the formation of a wiring groove pattern (e.g., refer to Japanese Laid Open (Kokai) 2004-319616, in particular, FIGS. 1 to 6 and paragraph numbers (0056) to (0078)).
However, in such a manufacturing method which first produces the wiring groove, both the wiring groove pattern and the via pattern are aligned with a lower embedded wiring line, so that the wiring groove and a via are indirectly aligned. Therefore, a margin between the adjacent via and wiring line may decrease depending on the amounts and directions of displacement in their alignments. This is explained in specific terms taking the manufacturing method in Japanese Laid Open (Kokai) 2004-319616 as an example.
In the manufacturing method in Japanese Laid Open (Kokai) 2004-319616, the thickness of a step of a foundation layer is reduced to about 50 nm to increase the accuracy of a resist mask having a via pattern (refer to paragraph number (0062) and FIG. 3(c)), so that even if a via pattern 14′ is to be aligned with an already formed wiring groove pattern 10′ for an upper embedded wiring line, it is not possible to obtain an adequate alignment signal because an alignment mark of the wiring groove pattern formed on a dicing line on the periphery of a chip is formed at the same thickness (about 50 nm). As a via connects a lower embedded wiring line 28 and the upper embedded wiring line, the via pattern 14′ has to be aligned with the lower embedded wiring line 28 if it can not be aligned with the upper embedded wiring line. Thus, the via pattern 14′ is aligned with the lower embedded wiring line 28 using an alignment mark of the lower embedded wiring line 28 formed on the dicing line simultaneously with the lower embedded wiring line 28. When, for example, the directions of misalignments at this point are opposite to each other and the amounts of the misalignments are great, a margin between the via and the adjacent upper embedded wiring line of a different potential becomes small in a manufactured semiconductor device, so that there has been a problem of a possible short circuit trouble occurring between the via and wiring line that are adjacent to each other.
FIGS. 16A and 16B are diagrams explaining the disadvantage of the dual damascene method according to the above-mentioned conventional art which first produces the wiring groove pattern. FIG. 16A is a partial plan view of one example of a wiring structure formed by the conventional art, and FIG. 16B is a sectional view along the A-A line in FIG. 16A.
As shown in FIGS. 16A and 16B, upper embedded wiring lines M21, M22 are shifted by ST1 to the right in FIGS. 16A and 16B with respect to lower embedded wiring lines M11, M12, while a via pattern V2 is shifted by ST2 or more to the left in FIGS. 16A and 16B with respect to the lower embedded wiring line M11. As a result, a margin MG between the via pattern V2 and the adjacent upper embedded wiring line M22 of a different potential is extremely narrow.
Such a problem is more evident when the distance between wiring lines is more reduced due to the advanced miniaturization of wiring lines.